1. Field of the Invention
The present invention relates to a semiconductor device (SOI device) comprising an SOI (Silicon On Insulator) substrate and a semiconductor element formed on the SOI substrate, and a method of manufacturing the semiconductor device.
2. Description of the Background Art
In recent years, attention has been paid to the SOI device because it can be utilized as a high speed device having low power consumption. The SOI substrate includes a substrate formed of silicon or the like, a buried insulating film such as an oxide film which is formed on the substrate and a silicon layer formed on the buried insulating film. A semiconductor element is formed on at least one of the inner portion or surface of the silicon layer in the SOI substrate. Consequently, the SOI device functions as a semiconductor device.
In recent years, particularly, attention has been paid to a so-called thin film SOI device in which a silicon layer in an SOI substrate has a small thickness of approximately several xcexcm. The application of the thin film SOI device to an LSI for portable equipment and the like has been expected.
FIG. 45 shows an example of a conventional SOI device. In FIG. 45, the reference numeral 1 denotes a substrate constituting the SOI substrate, the reference numeral 2 denotes a buried insulating film constituting the SOI substrate, and the reference numeral 3a denotes a part of a silicon layer constituting the SOI substrate. A plurality of MOS transistors TR1 are formed as an example of the semiconductor element in the silicon layer 3a and on a surface thereof. By way of example, the MOS transistor TR1 is an n-channel type. In order to function as a body region and a channel formation region, the silicon layer 3a is provided with a well in which a p-type impurity is injected, for example.
The MOS transistor TR1 includes a drain region 6a and a source region 6b which are formed in the silicon layer 3a and a gate insulating film 4a and a gate electrode 7a which are formed on a surface of the silicon layer 3a. The gate insulating film 4a is an insulating film such as an oxide film, and the gate electrode 7a is a conductive film such as polysilicon or a metal film. The silicon layer 3a interposed between the drain region 6a and the source region 6b functions as a body region of the MOS transistor TR1. In order to reduce a resistance, silicide regions 9a, 10a and 10b such as CoSi or TiSi are formed on surfaces of the gate electrode 7a, the drain region 6a and the source region 6b, respectively. A side wall 8 which has been used for forming an extension region in the drain region 6a and the source region 6b is formed on a side surface of the gate electrode 7a. As an example, FIG. 45 shows the case in which the drain region 6a and the source region 6b are provided deeply in contact with the buried insulating film 2.
Furthermore, an isolating film 5a comprising an insulating film such as an oxide film is formed between the MOS transistors TR1 in order to electrically isolate the elements. The isolating film 5a is formed in contact with the buried insulating film 2 perfectly through the silicon layer in order to electrically isolate the elements completely . With such a structure, latch up free is obtained and a tolerance to noises is enhanced. For distinction from a partial isolating film which will be described below, the insulating film will be hereinafter referred to as a complete isolating film.
The MOS transistor formed on an ordinary bulk substrate in place of the SOI substrate is used by applying a body voltage (for example, a ground potential) to the bulk substrate to be a body region. However, in the case of the SOI device shown in FIG. 45, each MOS transistor TR1 is electrically insulated completely from the substrate 1 through the buried insulating film 2 and the complete isolating film 5a and the silicon layer 3a of the body region is set in an electrical floating state. For this reason, floating-body problems arise, which are negligible in the MOS transistor formed on the bulk substrate.
As one of the floating-body problems, a humup (a bump-shaped step portion) is generated in current-voltage characteristics of a drain-source current Ids and a drain-source voltage Vds, that is, a so-called kink effect is caused. FIG. 46 is a chart showing the kink effect. As shown in FIG. 46, a hump HP is generated in a portion to have a constant current characteristic in a current-voltage characteristic of an ordinary transistor.
It is supposed that the hump HP is generated due to a hole HL accumulated in the vicinity of the source region 6b shown in FIG. 47. The hole HL is generated due to the impact ionization phenomena, and is accumulated in the vicinity of the source region 6b and a pn junction between a body and a source is forward biased. If the body voltage is applied to the body region, such a problem arises with difficulty.
Moreover, it is supposed that other causes of the generation of the hump HP include a parasitic bipolar transistor PT shown in FIG. 47 in which the drain region 6a, the source region 6b and the silicon layer 3a of the body region are set to be a collector, an emitter and a base, respectively. In addition to the kink effect, the parasitic bipolar transistor PT causes a drop in a breakdown voltage between a drain and a source, abnormal sharpness of inclination of subthreshold characteristics, an increase in a current during OFF, a drop in a threshold voltage, the generation of frequency dependency in a delay time and the like. These problems can be solved if the body voltage is applied to the body region.
Recently, a reduction in current drivabilities has also been reported as another floating-body problem (Extended Abstracts of the 1999 International Conference on Solid State Devices and Materials, Tokyo, 1999, pp. 340-341).
In order to solve such a floating-body problem, an impurity concentration of a channel portion in the body region should be increased. However, a rise in the impurity concentration increases a substrate bias effect. Consequently, the current drivabilities are reduced.
In the SOI device, moreover, reliability on hot carriers is also a matter of concern. In the case of the MOS transistor, when the silicon layer of the SOI substrate by has a very small thickness, hot carriers generated in a high electric-field region in the vicinity of a drain region are also injected into a buried insulating film as well as a gate insulating film. Consequently, the device is greatly deteriorated. The problem of the hot carriers is also important for the MOS transistor formed on the bulk substrate. In the MOS transistor formed on the SOI substrate, two insulating films, that is, the gate insulating film and the buried insulating film are provided. Therefore, the problem of the hot carriers is more serious.
In order to solve the floating-body problem and the hot carrier problem described above, it is preferable that an electric potential of the body region should be fixed electrically. In the SOI device shown in FIG. 45, each MOS transistor TR1 is electrically insulated completely from the substrate 1 through the buried insulating film 2 and the complete isolating film 5a. With this structure, accordingly, a body terminal connected electrically to the body region should be provided on a surface of the SOI substrate and a body voltage should be applied thereto in order to control the body potential to the silicon layer 3a of the body region.
However, if the body terminal is provided on all the MOS transistors in an integrated circuit, a circuit area is greatly increased.
Consequently, it has been proposed that a partial isolating film which does not reach the buried insulating film is employed in place of the complete isolating film 5a. If the isolating film does not reach the buried insulating film, it is sufficient that one body terminal should be provided on the surface of the SOI substrate in a proper portion because the body regions of the MOS transistors are electrically connected to each other.
FIGS. 48 to 50 are views showing the case in which the partial isolating film is applied to the SOI device illustrated in FIG. 45. FIG. 48 is a top view showing the SOI device, FIG. 49 is a sectional view taken along the line X7xe2x80x94X7 in FIG. 48, and FIG. 50 is a sectional view taken along the line Yxe2x80x94Y in FIG. 48.
In the SOI device shown in FIGS. 49 and 50, a partial isolating film 5b is formed between the MOS transistors TR1 in place of the complete isolating film 5a of the SOI device shown in FIG. 45. The silicon layer 3b is not completely removed but remains between the partial isolating film 5b and the buried insulating film 2. As is apparent from FIG. 50, the silicon layer 3b provided under the partial isolating film 5b and the silicon layer 3a of the body region of the MOS transistor TR1 belong to the same well and are electrically connected to each other.
On the other hand, a body terminal region 3d shown in FIG. 48 also belongs to the same well as the silicon layers 3a and 3b, and is electrically connected thereto. Accordingly, a body voltage Vbd is applied to the body terminal region 3d so that the electric potentials of the silicon layers 3a and 3b are fixed to the body voltage Vbd. Consequently, the floating-body problem and the hot carrier problem can be solved.
In the SOI substrate employing the partial isolating film, an advantage such as latch up free obtained by the conventional SOI substrate employing the complete isolating film is eliminated. In the case in which an impurity is previously injected into a silicon layer to provide a plurality of wells having different conductivity types, it can also be proposed that the partial isolating film is employed only in a well of the homogeneous conductivity type and the complete isolating film is employed for a boundary region between wells of different conductivity types.
If it is not necessary to take the latch up problem and the like into consideration, only the partial isolating film can be used. Consequently, it is not necessary to manufacture the insulating films of both types. Thus, the number of steps required for the manufacture can be decreased.
However, the silicon layer 3b provided under the partial isolating film 5b has a small thickness. Consequently, a value of a resistance RS is easily increased. In particular, as the position of the MOS transistor TR1 is more distant from the body terminal region 3d, a value of a resistance therebetween is increased. Consequently, it is hard to control the body potential all over the semiconductor device.
Consequently, the floating-body problem and the hot carrier problem cannot be solved satisfactorily. Moreover, the characteristics of the semiconductor element are varied depending on a distance from the body terminal region.
As shown in FIG. 51, for example, if the drain region 6a and the source region 6b of the MOS transistor TR1 are provided in no contact with the buried insulating film 2, the silicon layer 3b is conducted to the silicon layer 3a of the body region under the drain region 6a and the source region 6b. Consequently, the floating-body problem and the hot carrier problem can be somewhat solved. However, the above-mentioned problems cannot be solved satisfactorily.
In the partial isolating film 5b which is widely distributed, a great tensile stress is applied to the drain region 6a and the source region 6b which are adjacent to the silicon layer 3b provided under the partial isolating film 5b and the partial isolating film 5b. In FIG. 49, the tensile stress is indicated as ST2. The tensile stress ST2 is caused by a change in a volume of the partial isolating film 5b due to heat during the formation of the partial isolating film 5b and a difference in a coefficient of thermal expansion between the silicon layer 3b and the partial isolating film 5b. In the partial isolating film 5b which is widely distributed, the volume is greatly changed. Consequently, peripheral structures are greatly influenced.
If the tensile stress ST2 is great, a crystal defect is generated on the silicon layer 3b, the drain region 6a and the source region 6b. As a result, there is a possibility that a leakage current in a well might be increased. In particular, since the silicon layer 3b has a small thickness, the crystal defect is easily generated.
Also in the case in which the partial isolating film and the complete isolating film are used together, the floating-body problem, the hot carrier problem and the crystal defect problem may arise.
It is an object of the present invention to satisfactorily solve a floating-body problem and a hot carrier problem which often arise in an SOI device and to provide a semiconductor device in which a widely distributed partial isolating film generates a crystal defect for peripheral structures with difficulty and a method of manufacturing the semiconductor device.
A first aspect of the present invention is directed to a semiconductor device comprising an SOI substrate having a substrate, a buried insulating film formed on the substrate, and a semiconductor layer formed on the buried insulating film, a partial isolating film to be an insulating film formed in the vicinity of a surface of the semiconductor layer in no contact with the buried insulating film, a semiconductor element formed including a part of the semiconductor layer, and a dummy region having no function as an element which interposes the partial isolating film with the semiconductor element and is formed including another part of the semiconductor layer.
A second aspect of the present invention is directed to the semiconductor device according to the first aspect of the present invention, further comprising a complete isolating film to be an insulating film formed in contact with the buried insulating film through the semiconductor layer, and a dummy region having no function as an element which interposes the complete isolating film with the semiconductor element and is formed including another part of the semiconductor layer.
A third aspect of the present invention is directed to the semiconductor device according to the first or second aspect of the present invention, wherein an impurity of a predetermined conductivity type is injected into the semiconductor layer of the dummy region.
A fourth aspect of the present invention is directed to the semiconductor device according to the third aspect of the present invention, wherein a well of the predetermined conductivity type is formed in the semiconductor layer, and the semiconductor layer of the dummy region is a part of the well.
A fifth aspect of the present invention is directed to the semiconductor device according to any of the first to fourth aspects of the present invention, wherein a dummy wiring is connected to a surface of the semiconductor layer of the dummy region.
A sixth aspect of the present invention is directed to the semiconductor device according to the third aspect of the present invention, wherein the dummy region includes a dummy gate having a dummy gate insulating film formed on a surface of the another part of the semiconductor layer and a dummy gate electrode formed on the dummy gate insulating film.
A seventh aspect of the present invention is directed to the semiconductor device according to the sixth aspect of the present invention, wherein a fixed voltage is applied to the dummy gate electrode.
An eighth aspect of the present invention is directed to the semiconductor device according to the sixth aspect of the present invention, wherein the dummy gate is partially provided on the another part of the semiconductor layer, and an impurity of the predetermined conductivity type is injected into a portion of the another part of the semiconductor layer which is not covered with the dummy gate.
A ninth aspect of the present invention is directed to the semiconductor device according to the eighth aspect of the present invention, further comprising a dummy contact plug electrically connected to the semiconductor layer and the dummy gate electrode in the dummy region, and a dummy wiring connected to the dummy contact plug.
A tenth aspect of the present invention is directed to the semiconductor device according to the sixth aspect of the present invention, wherein the dummy gate has a cross shape, and the semiconductor layer of the dummy region constitutes a parallelogram having four sides parallel with each side forming the cross shape of the dummy gate.
An eleventh aspect of the present invention is directed to a method of arranging a dummy region comprising the steps of (a) preparing a first pattern in which a plurality of dummy regions are regularly arranged, (b) preparing a second pattern in which each of a pattern of an element and a circuit or a pattern of a well is described, and (c) superposing the first and second patterns to erase the dummy region in a portion superposed on the element and the circuit or a boundary portion of the well, thereby determining an arrangement of the dummy regions.
A twelfth aspect of the present invention is directed to the method of arranging a dummy region according to the eleventh aspect of the present invention, wherein the arrangement of the dummy region is determined by erasing the dummy region present around the pattern in addition to the dummy region in a portion superposed on the pattern at the step (c).
A thirteenth aspect of the present invention is directed to the method of arranging a dummy region according to the twelfth aspect of the present invention, wherein another dummy region having a different size from a size of the dummy region is newly provided in a position where the dummy region is erased such that it is not superposed on the pattern at the step (c).
A fourteenth aspect of the present invention is directed to a method of manufacturing a semiconductor device comprising the steps of (a) preparing an SOI substrate having a substrate, a buried insulating film formed on the substrate, and a semiconductor layer formed on the buried insulating film, (b) forming a partial isolating film to be an insulating film in no contact with the buried insulating film in the vicinity of a surface of the semiconductor layer, (c) forming a semiconductor element in the semiconductor layer, and (d) forming a dummy region having no function as an element in the semiconductor layer while interposing the partial isolating film with the semiconductor element simultaneously with the step (c).
According to the first aspect of the present invention, the dummy region is provided. Therefore, a floating-body problem and a hot carrier problem can be solved more satisfactorily than the case in which the partial isolating film is continuously provided. Furthermore, a tensile stress of the partial isolating film can be distributed over the dummy region and force applied to the semiconductor element or the like through the tensile stress can be reduced. Moreover, the provision of the dummy region can enhance the stability of a forming process for the partial isolating film.
According to the second aspect of the present invention, the dummy region is provided. Therefore, a tensile stress of the complete isolating film can be distributed over the dummy region and force applied to the semiconductor element or the like through the tensile stress can be reduced. Moreover, the provision of the dummy region can enhance the stability of a forming process for the complete isolating film. Furthermore, the complete isolating film is provided. Therefore, a tolerance to latch up and noises is great.
According to the third aspect of the present invention, the impurity of the predetermined conductivity type is injected into the semiconductor layer of the dummy region. Therefore, a value of a resistance between the semiconductor element and a portion to which a body voltage is applied can be prevented from being increased. Accordingly, the body potential can be controlled all over the semiconductor device, and the floating-body problem and the hot carrier problem can be solved. Consequently, it is possible to prevent the characteristics of the semiconductor element from being varied depending on a distance from a body terminal region.
According to the fourth aspect of the present invention, a resistance value of the dummy region can be more reduced than that in the case in which the well and the semiconductor layer of the dummy region have conductivity types different from each other.
According to the fifth aspect of the present invention, the dummy wiring is connected to the surface of the semiconductor layer of the dummy region. Therefore, the body potential can be controlled more easily all over the semiconductor device and the floating-body problem and the hot carrier problem can be solved more reliably. Moreover, in the case in which an interlayer insulating film is provided between the dummy wirings and an upper interlayer insulating film is further formed thereon and is subjected to a CMP method, dishing is caused on the upper interlayer insulating film with difficulty. Furthermore, it is possible to eliminate a self-heating effect which often makes troubles in an SOI device.
According to the sixth aspect of the present invention, the dummy gate electrode is provided. Therefore, in the case in which the semiconductor element having a gate electrode is to be formed by photolithography or the like, it is possible to prevent a variation in a dimension of the gate electrode from being generated. Furthermore, in the case in which the interlayer insulating film is formed in upper portions of the semiconductor element and the dummy region and is subjected to the CMP method, the dishing is caused on the interlayer insulating film with difficulty.
According to the seventh aspect of the present invention, a dummy gate voltage is applied to the dummy gate electrode. Therefore, the resistance value of the semiconductor layer can be more reduced.
According to the eighth aspect of the present invention, the dummy gate is partially provided on another part of the semiconductor layer and the impurity of the predetermined conductivity type is injected into the portion of another part of the semiconductor layer which is not covered with the dummy gate. Therefore, the effects of the semiconductor devices according to the third and sixth aspects of the present invention can be obtained at the same time.
According to the ninth aspect of the present invention, the semiconductor layer of the dummy region and the dummy gate electrode can be connected electrically. Therefore, the resistance value of the dummy region can be fixed. Moreover, the electrical connection is carried out by using the dummy contact plug and the dummy wiring. Therefore, the body potential can be controlled more easily all over the semiconductor device and the floating-body problem and the hot carrier problem can be solved more reliably. Moreover, in the case in which an interlayer insulating film is provided between the dummy wirings and an upper interlayer insulating film is further formed on the interlayer insulating film and is subjected to a CMP method, dishing is caused on the upper interlayer insulating film with difficulty because the dummy wiring is provided. Furthermore, it is possible to eliminate a self-heating effect which often makes troubles in the SOI device.
According to the tenth aspect of the present invention, the dummy gate has the cross shape, and the semiconductor layer of the dummy region constitutes a parallelogram having four sides parallel with each side forming the cross shape of the dummy gate. Therefore, also in the case in which the pattern of the dummy gate is shifted, the resistance value of the dummy region is not changed. Thus, the dummy region can have a resistance value which is rarely influenced by the stability of the process.
According to the eleventh aspect of the present invention, the dummy region in the portion superposed on the element and the circuit or the boundary portion of the well is erased. Consequently, the element and the circuit or the well can be prevented from being short-circuited through the dummy region.
According to the twelfth aspect of the present invention, not only the dummy region in the portion superposed on the patterns of the element and the circuit or the boundary portion of the well but also the dummy region existing therearound is erased. Therefore, the element and the circuit or the well can be more prevented from being short-circuited through the dummy region.
According to the thirteenth aspect of the present invention, another dummy region having a different size from the size of the dummy region is newly provided in the position where the dummy region is erased such that it is not superposed on the pattern. Therefore, the isolating film can have a uniform density and the dummy region is effective in the stability of the process such as a CMP.
According to the fourteenth aspect of the present invention, the semiconductor element and the dummy region are formed at the same time. Therefore, a new step of providing the dummy region is not required and a layout of a conventional photomask is only changed, which is economical.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.